Method for fabricating lightly doped drain area, thin film transistor and array substrate

ABSTRACT

Embodiments of the disclosure provide a method for fabricating a lightly doped drain area, a thin film transistor, and a thin film transistor array substrate. In an embodiment of the disclosure, a poly-silicon layer, a gate insulation layer, and a gate metal layer are formed in sequence on a substrate; the gate metal layer is patterned to form a gate electrode; the gate insulation layer is etched to form a stepped structure, wherein a width of the gate electrode is smaller than a width of the stepped structure, and an edge of the stepped structure is not covered by the gate electrode; and the poly-silicon layer is doped by an ion doping process using the gate electrode and the gate insulation layer with the stepped structure as a mask to form both a lightly doped area and a heavily doped area.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority to Chinese Patent Application No.201410851974.0, filed Dec. 31, 2014, the content of which is herebyincorporated by reference in its entirety.

FIELD

The present disclosure relates to the field of liquid crystal displaysand particularly to a method for fabricating a lightly doped drain area,a thin film transistor, and a thin film transistor array substrate.

BACKGROUND

A demand for a panel with high resolution and low power consumption hasbeen proposed constantly along with the development of a flat paneldisplay. Low Temperature Poly-Silicon (LTPS) has been widely applied toa Liquid Crystal Display (LCD) and an Organic Light Emitting Diode(OLED) display due to its high mobility of electrons. In the LTPStechnology, a Lightly Doped Drain (LDD) is commonly adopted to suppressleakage current rising abnormally. FIG. 1a and FIG. 1b illustrateschematic sectional views of a device in an existing method for formingan LDD area. As illustrated in FIG. 1 a, after a buffer layer 102 and apoly-silicon layer 103 are formed in sequence on a substrate 101, aphoto-resist layer 104 is applied on the poly-silicon layer 103 andpatterned. An area of the poly-silicon layer 103, which is not coveredby the photo-resist layer 104, is doped by an ion doping process, sothat the area which is not covered by the photo-resist layer 104 can besubsequently doped for a second time into a heavily doped drain area. Asillustrated in FIG. 1 b, after the poly-silicon layer 103 is doped forthe first time, a gate insulation layer and a gate metal layer areformed in sequence on the doped poly-silicon layer, and the gate metallayer is patterned to form a gate electrode 106. An injection area isdefined using the gate electrode 106 as a mask through self-alignment ofthe gate electrode 106, and an area which is not covered by the gateelectrode 106 is doped by an ion doping process, resulting in a lightlydoped drain area 107 and a heavily doped drain area 108.

In summary, the LDD area has to be formed at present by two ion dopingprocesses, thus complicating the preparation procedure, and it may notbe easy to control the precision of a junction depth in the formed LDDarea due to an error in alignment using the mask by two patterningprocesses.

SUMMARY

Embodiments of the disclosure disclose a method for fabricating alightly doped drain area, a thin film transistor, and a thin filmtransistor array substrate.

An embodiment of the disclosure discloses a method for fabricating alightly doped drain area, the method including:

-   -   forming a poly-silicon layer, a gate insulation layer, and a        gate metal layer in sequence on a substrate;    -   patterning the gate metal layer to form a gate electrode;    -   etching the gate insulation layer to form a stepped structure,        wherein a width of the gate electrode is smaller than a width of        the stepped structure, and an edge of the stepped structure is        not covered by the gate electrode; and    -   doping the poly-silicon layer by a doping process using the gate        electrode, and the gate insulation layer with the stepped        structure as a mask to form a lightly doped area and a heavily        doped area.

An embodiment of the disclosure further discloses a Thin Film Transistor(TFT) including the lightly doped drain area fabricated by thefabricating method above, the TFT including:

-   -   a substrate, a poly-silicon layer, a gate insulation layer with        a stepped structure, and a gate electrode formed in sequence on        the substrate,    -   wherein a width of the gate electrode is smaller than a width of        the stepped structure, and an edge of the stepped structure is        not covered by the gate electrode; and    -   a width of the lightly doped area is equal to a width of an area        of the stepped structure not covered by the gate electrode.

An embodiment of the disclosure further discloses a thin film transistorarray substrate including the thin film transistor above.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1a and FIG. 1b illustrate schematic sectional views of a device ina method for forming an LDD area in the prior art;

FIG. 2 illustrates a schematic flow chart of a method for fabricating anLDD area according to an embodiment of the disclosure;

FIG. 3a to FIG. 3e illustrate a flow chart of a process of fabricatingan LDD area according to an embodiment of the disclosure;

FIG. 4 illustrates a schematic flow chart of a method for fabricating anLDD area according to an embodiment of the disclosure;

FIG. 5a to FIG. 5e illustrate a flow chart of a process of fabricatingan LDD area according to an embodiment of the disclosure;

FIG. 6 illustrates a comparison diagram of current when a TFT is turnedoff, where the drain area of the TFT is formed through a gate insulationlayer with a stepped structure or a gate insulation layer without astepped structure; and

FIG. 7 illustrates a schematic diagram of a TFT array substrateaccording to an embodiment of the disclosure.

DETAILED DESCRIPTION OF THE EMBODIMENTS

In order to make the objects, technical solutions and advantages of thedisclosure more apparent, the disclosure will be described below infurther details with reference to the drawings, and evidently theembodiments described here are merely a part but not all of theembodiments of the disclosure. All the other embodiments which can occurto those ordinarily skilled in the art based upon the embodiments hereof the disclosure without any inventive effort shall fall into the scopeof the disclosure as claimed.

FIG. 2 illustrates a schematic flow chart of a method for fabricating alightly doped drain area according to an embodiment of the disclosure,where the method includes step 201 to step 204:

Step 201 is to form a poly-silicon layer, a gate insulation layer, and agate metal layer in sequence on a substrate;

Step 202 is to pattern the gate metal layer to form a gate electrode;

Step 203 is to etch the gate insulation layer to form a steppedstructure, where the width of the gate electrode is smaller than thewidth of the stepped structure, and the edge of the stepped structure isnot covered by the gate electrode; and

Step 204 is to dope the poly-silicon layer by an ion doping processusing the gate electrode, and the gate insulation layer with the steppedstructure as a mask to form both a lightly doped area and a heavilydoped area.

Particularly firstly the substrate 301 can be cleared by an initialclearing process as illustrated in FIG. 3a before step 201. In order toprevent an adverse influence of harmful substances in the substrate 301,e.g., alkali metal ions, on the performance of the poly-silicon layer303, a buffer layer 302 can be deposited on the substrate 301 by aPlasma Enhanced Chemical Vapor Deposition (PECVD) process, and thesubstrate 301 needs to be pre-cleaned before the buffer layer 302 isdeposited. The prepared buffer layer 302 can be annealed for a higherquality of the buffer layer 302.

In step 201, an amorphous silicon layer can be deposited on the bufferlayer 302 by a PECVD process and dehydrogenated in an oven at hightemperature to thereby prevent hydrogen explosion during crystallizationand lower a defect density in the silicon layer after crystallization.The dehydrogenated amorphous silicon layer is poly-crystallized by a LowTemperature Poly-Silicon (LTPS) process. The amorphous silicon layer iscrystallized typically by an Excimer Laser Annealing (ELA) process, aMetal Induced Crystallization (MIC) process, a Solid PhaseCrystallization (SPC), etc., to form the poly-silicon layer 303. Thesurface of the poly-silicon layer 303 is treated so that the roughnesson the surface of the poly-silicon layer 303 can be lowered andirregularities, protrusions, etc., arising from crystallization can beremoved, thus the poly-silicon layer 303 can come into better contactwith the subsequent thin film layer, thereby improving the performanceof the entire device.

The gate insulation layer 304 in the embodiment of the disclosureincludes a silicon nitride layer or a silicon oxide layer. The siliconnitride layer or the silicon oxide layer is formed on the poly-siliconlayer 303 by a PECVD process to form the gate insulation layer 304.

In step 202, as illustrated in FIG. 3 b, photo-resist 306 is applied onthe gate metal layer, exposed using a mask and developed into apreliminary gate electrode pattern; and the gate metal layer 305 isetched by a dry etching process to form a preliminary gate electrode 305a.

As illustrated in FIG. 3 c, the preliminary gate electrode is etched bya wet etching process to form the gate electrode 305 b while keeping thephoto-resist 306 on the surface of the preliminary gate electrode, wherethe gate insulation layer 304 is not etched by the wet etching processwhile the preliminary gate electrode is etched.

In step 203, as illustrated in FIG. 3 c, the surface of the gateinsulation layer is etched by a dry etching process to form a gateinsulation layer 304 a with a stepped structure p after the gateelectrode 305 b is formed. Optionally the thickness of an area of thegate insulation layer 304 a other than the stepped structure p issmaller than 800 angstroms. When the surface of the gate insulationlayer is etched to form the stepped structure p, the etched area of thegate insulation layer is an area other than the area overlapped with thephoto-resist 306, where the width of the gate electrode 305 b is smallerthan the width of the stepped structure p, and the edge of the steppedstructure p is not covered by the gate electrode.

In the embodiment of the disclosure, as illustrated in FIG. 3 c, thegate electrode 305 b can be formed by controlling the etched amount, bywhich the preliminary gate electrode is pushed in, to thereby adjust thewidth L1 of the area of the stepped structure p not covered by the gateelectrode 305 b.

As illustrated in FIG. 3 d, in step 204, the poly-silicon layer 303 isdoped by an ion doping process using the gate electrode 305 b, and thegate insulation layer 304 a with the stepped structure as a mask. In theion doping process, the area of the poly-silicon layer 303 covered bythe gate electrode 305 b will not be doped due to being shielded by thegate electrode 305 b, whereas the area of the poly-silicon layer 303 notcovered by the gate electrode 305 b will be doped. Respective parts ofthe gate insulation layer 304 a with the stepped structure p on thepoly-silicon layer 303 vary in thickness, the thickness of the area ofthe stepped structure p is larger than the thickness of the area otherthan the stepped structure, and the gate insulation layer 304 a varyingin thickness applies varying shielding, so the doped concentration ofthe area of the poly-silicon layer corresponding to the gate insulationlayer 304 a at different thicknesses may be different. As illustrated inFIG. 3 e, the lightly doped drain area 307 is formed in the areacorresponding to the stepped structure p, and the heavily doped drainarea 308 is formed in the area corresponding to the gate insulationlayer other than the stepped structure, where the width of the lightlydoped drain area 307 is equal to the width of the area of the steppedstructure p not covered by the gate electrode 305 b. Optionally firstlythe remaining photo-resist can be removed before step 204.

In the embodiment of the disclosure, as illustrated in FIG. 3 c, thewidth L1 of the area of the stepped structure p not covered by the gateelectrode 305 b is adjusted so that the width of the formed lightlydoped drain area 307 can be controlled flexibly. The stepped structure pcan be formed by controlling the etched thickness to thereby adjust thethickness H1 of the stepped structure and further strengthen or weakenshielding of the gate insulation layer against doping, so that the dopedconcentration of the formed lightly doped drain area 307 can becontrolled flexibly.

Optionally the poly-silicon layer is an un-doped poly-silicon layerbefore the poly-silicon layer is doped and the LDD area is formed.Optionally the width of the area of the stepped structure not covered bythe gate electrode is equal to an expected width of the lightly dopeddrain area.

In an embodiment of the disclosure, the poly-silicon layer, the gateinsulation layer, and the gate metal layer are formed in sequence on thesubstrate; the gate metal layer is patterned to form the gate electrode;the gate insulation layer is etched to form the stepped structure, wherethe width of the gate electrode is smaller than the width of the steppedstructure, and the edge of the stepped structure is not covered by thegate electrode; and the poly-silicon layer is doped by the ion dopingprocess using the gate electrode and the gate insulation layer with thestepped structure as the mask to form both the lightly doped area andthe heavily doped area. In the embodiment of the disclosure, since thewidth of the gate electrode is smaller than the width of the steppedstructure, and the edge of the stepped structure is not covered by thegate electrode, the LDD area can be formed by only one ion dopingprocess, and the height and the width of the stepped structure can bevaried to thereby adjust flexibly the doped concentration and the sizeof the LDD area so as to alleviate leakage current effectively.

Referring to FIG. 4, it illustrated a schematic flow chart of a methodfor fabricating a lightly doped drain area according to an embodiment ofthe disclosure, where the method includes step 401 to step 406; and alsoreferring to FIG. 5a to FIG. 5 e, they illustrated a flow chart of aprocess of preparing an LDD area according to an embodiment of thedisclosure:

Step 401 is to form a poly-silicon layer 503, a gate insulation layer504, and a gate metal layer 505 in sequence on a substrate 501;

Step 402 is to etch the gate metal layer 505 by a first etching processto form a preliminary gate electrode 505 a;

Step 403 is to etch the gate insulation layer 504 for a first time bythe first etching process to form a preliminary stepped structure p1;

Step 404 is to etch the preliminary gate electrode 505 a by a secondetching process to form a gate electrode 505 b while keepingphoto-resist 506 on the surface of the preliminary gate electrode 505 a;

Step 405 is to etch the gate insulation layer 504 for a second time bythe first etching process to form a final stepped structure p2, wherethe width of the gate electrode 505 b is smaller than the width of thestepped structure p, and the edge of the stepped structure p2 is notcovered by the gate electrode 505 b;

Step 406 is to dope the poly-silicon layer 503 by an ion doping processusing the gate electrode 505 b and the gate insulation layer 504 a withthe stepped structure p2 as a mask to form both a lightly doped area 507and a heavily doped area 508.

Particularly firstly the substrate 501 can be cleared by an initialclearing process as illustrated in FIG. 5a before step 401. In order toprevent an adverse influence of harmful substances in the substrate 501,e.g., alkali metal ions, on the performance of the poly-silicon layer503, a buffer layer 502 can be deposited on the substrate 501 by a PECVDprocess, and the substrate 501 needs to be pre-cleaned before the bufferlayer 502 is deposited. The prepared buffer layer 502 can be annealedfor a higher quality of the buffer layer 502.

In step 401, an amorphous silicon layer can be deposited on the bufferlayer 502 by a PECVD process and dehydrogenated in an oven at hightemperature to thereby prevent hydrogen explosion during crystallizationand low a defect density in the silicon layer after crystallization. Thedehydrogenated amorphous silicon layer is poly-crystallized by a LowTemperature Poly-Silicon (LTPS) process. The amorphous silicon layer iscrystallized typically by an Excimer Laser Annealing (ELA) process, aMetal Induced Crystallization (MIC) process, a Solid PhaseCrystallization (SPC), etc., into the poly-silicon layer 503. Thesurface of the poly-silicon layer 503 is treated so that the roughnesson the surface of the poly-silicon layer 503 can be lowered by removingirregularities, protrusions, etc., arising from crystallization so thatthe poly-silicon layer 503 can come into better contact with thesubsequent thin film layer to thereby improve the performance of theentire device.

The gate insulation layer 504 in the embodiment of the disclosureincludes a silicon nitride layer or a silicon oxide layer. The siliconnitride layer or the silicon oxide layer is formed on the poly-siliconlayer 503 by a PECVD process resulting in the gate insulation layer 504.

In step 402, as illustrated in FIG. Sb, photo-resist 506 is applied onthe gate metal layer, exposed using a mask and developed into apreliminary gate electrode pattern; and the gate metal layer is etchedby a dry etching process to form a preliminary gate electrode 505 a.

In step 403, as illustrated in FIG. Sb, the gate insulation layer 504 isetched for a first time by a dry etching process to form the preliminarystepped structure p1.

In step 404, as illustrated in FIG. Sc, the preliminary gate electrodeis etched by a wet etching process to form a gate electrode 505 b whilekeeping the photo-resist 506 on the surface of the preliminary gateelectrode.

In step 405, as illustrated in FIG. Sc, the gate insulation layer isetched for a second time by a dry etching process to form the finalstepped structure p2. Optionally the thickness of an area of the gateinsulation layer 504 a with the stepped structure p2 other than thestepped structure p2 is smaller than 800 angstroms. The preliminarystepped structure p1 can be etched for the second time to therebyfurther adjust the height of the stepped structure so as to control thedoped concentration of the formed LDD area. Alternatively the secondetching may not be performed if the thickness of the preliminary steppedstructure pl formed by the first etching process is as expected.

Where the width of the gate electrode 505 b is smaller than the width ofthe stepped structure p2, and the edge of the stepped structure p2 isnot covered by the gate electrode 505 b. Optionally in the embodiment ofthe disclosure, the etching rate of the second etching is lower than theetching rate of the first etching. The first etching process can beperformed at a higher etching rate to thereby improve the efficiency ofetching effectively, and the preliminary stepped structure p1 can befurther adjusted in the second etching performed at a lower etching ratefor a better effect of adjusting.

In step 406, as illustrated in FIG. 5 d, the poly-silicon layer 503 isdoped by an ion doping process using the gate electrode 505 b and thegate insulation layer 504 a with the stepped structure as a mask. In thedoping process, the area of the poly-silicon layer 503 covered by thegate electrode will not be doped, whereas only the area of thepoly-silicon layer 503 not covered by the gate electrode will be doped.The gate insulation layer with the stepped structure on the poly-siliconlayer 503 varies in thickness, and the thickness of the area of thestepped structure is larger than the thickness of the area other thanthe stepped structure, so the poly-silicon layer 503 will be dopeddifferently in concentration. As illustrated in FIG. 5 e, the lightlydoped drain area 507 is formed in the area corresponding to the steppedstructure, and the heavily doped drain area 308 is formed in the areacorresponding to the gate insulation layer other than the steppedstructure, where the width of the lightly doped drain area 507 is equalto the width of the area of the stepped structure not covered by thegate electrode 505 b. Optionally firstly the remaining photo-resist canbe removed before step 406.

In the embodiment of the disclosure, as illustrated in FIG. 5 c, thewidth L2 of the area of the stepped structure not covered by the gateelectrode 505 b is adjusted so that the width of the formed lightlydoped drain area 507 can be controlled flexibly. The stepped structurep2 can be formed by controlling the etched thickness to thereby adjustthe thickness H2 of the stepped structure p2, so that the dopedconcentration of the formed lightly doped drain area 507 can becontrolled flexibly.

Optionally the poly-silicon layer 503 is an un-doped poly-silicon layerbefore the poly-silicon layer is doped and the LDD area is formed.Optionally the width of the area of the stepped structure not covered bythe gate electrode is equal to the expected width of the lightly dopeddrain area.

The formation of the lightly doped drain area in an embodiment of thedisclosure will be described below with respect to the result of aparticular experiment. FIG. 6 illustrates a comparison diagram ofcurrent when a TFT is turned off, where the drain area of the TFT isformed through a gate insulation layer with a stepped structure or agate insulation layer without a stepped structure.

In this experiment, the lightly doped drain area is formed by the methodaccording to an embodiment of the disclosure, and further a TFT with thelightly doped drain area is fabricated. Also the drain area isfabricated by a similar process flow but without the stepped structure,and further a TFT without the lightly doped drain area is fabricated forthe comparative experiment. Boron ions are doped at an energy of 20 Kevand a dosage of 8E14, the gate insulation layer is consisted of asilicon oxide layer and a silicon nitride layer, and the height of thestepped structure (i.e., the thickness of the stepped structure) is 800angstroms including the 200 angstrom of the silicon oxide layer and the600 angstrom of the silicon nitride layer. In the experiment, aplurality of TFTs and a plurality of stepped structures in the pluralityof TFTs are formed, where the width of the plurality of steppedstructures ranges from 0.65 to 1.34 μm and is averaged as 0.79 μm. Forthe single-gate PTFT formed in the experiment, FIG. 6 illustratescomparison of drain current when the TFT is turned off in the case ofVd=−10V.

The upper curve in the figure represents the average of the current inthe OFF state, and as can be seen from the curve, the average of theleakage current when the TFT including the lightly doped drain areawhich is formed as a result of the stepped structure is turned off issignificantly smaller than the average of the leakage current when theTFT including no lightly doped drain area is turned off The lower curvein the figure represents the difference between the maximum and theminimum of the current in the OFF state, and as can be seen from thecurve, the uniformity of the leakage current when the TFT including thelightly doped drain area which is formed as a result of the steppedstructure is turned off is better than the uniformity of the leakagecurrent when the TFT including no lightly doped drain area is turnedoff.

In an embodiment of the disclosure, the lightly doped drain area and theheavily doped drain area are formed in the steps above, and since thewidth of the gate electrode is smaller than the width of the steppedstructure, and the edge of the stepped structure is not covered by thegate electrode, the LDD area can be formed by only one ion dopingprocess, and the height and the width of the stepped structure can bevaried to thereby adjust flexibly the doped concentration and the sizeof the LDD area so as to alleviate leakage current effectively.

An embodiment of the disclosure further provides a Thin Film Transistor(TFT) including the LDD area fabricated in the method according to theembodiments above of the disclosure, and further including:

A substrate, and a buffer layer, a poly-silicon layer, a gate insulationlayer with a stepped structure, a gate electrode, a source, and a draindisposed in sequence on the substrate,

where the width of the gate electrode is smaller than the width of thestepped structure, and the edge of the stepped structure is not coveredby the gate electrode; and

the LDD area is equal in width to an area of the stepped structure notcovered by the gate electrode.

FIG. 7 illustrates a schematic diagram of a TFT array substrateaccording to an embodiment of the disclosure, where the TFT arraysubstrate includes a plurality of the TFTs according to the embodimentabove of the disclosure and further includes a plurality of data lines701, a plurality of gate lines 702, and a pixel area 703 in which theTFTs are arranged.

As is apparent from the disclosure above, in the embodiments of thedisclosure, the poly-silicon layer, the gate insulation layer, and thegate metal layer are formed in sequence on the substrate; the gate metallayer is patterned to form the gate electrode; the gate insulation layeris etched to form the stepped structure, where the width of the gateelectrode is smaller than the width of the stepped structure, and theedge of the stepped structure is not covered by the gate electrode; andthe poly-silicon layer is doped by the ion doping process using the gateelectrode and the gate insulation layer with the stepped structure asthe mask to form both the lightly doped area and the heavily doped area.In the embodiments of the disclosure, since the width of the gateelectrode is smaller than the width of the stepped structure, and theedge of the stepped structure is not covered by the gate electrode, theLDD area can be formed by only one ion doping process, and the heightand the width of the stepped structure can be varied to thereby adjustflexibly the doped concentration and the size of the LDD area so as toalleviate leakage current effectively.

Although the preferred embodiments of the disclosure have beendescribed, those skilled in the art benefiting from the underlyinginventive concept can make additional modifications and variations tothese embodiments. Therefore the appended claims are intended to beconstrued as encompassing the optional embodiments and all thevariations and modifications falling into the scope of the disclosure.

Evidently those skilled in the art can make various modifications andvariations to the disclosure without departing from the spirit and scopeof the disclosure. Thus the disclosure is also intended to encompassthese modifications and variations thereto so long as the modificationsand variations fall into the scope of the claims appended to thedisclosure and their equivalents.

What is claimed is:
 1. A method for fabricating a lightly doped area,the method comprising: forming a poly-silicon layer, a gate insulationlayer, and a gate metal layer in sequence on a substrate; patterning thegate metal layer to form a gate electrode; etching the gate insulationlayer to form a stepped structure, wherein a width of the gate electrodeis smaller than a width of the stepped structure, and an edge of thestepped structure is not covered by the gate electrode; and doping thepoly-silicon layer by a doping process using the gate electrode and thegate insulation layer with the stepped structure as a mask to form alightly doped area and a heavily doped area.
 2. The method forfabricating a lightly doped area according to claim 1, wherein thepatterning the gate metal layer to form the gate electrode comprises:applying photo-resist on the gate metal layer, exposing the photo-resistusing a mask, and developing the photo-resist to form a preliminary gateelectrode pattern; etching the gate metal layer by a first etchingprocess to form a preliminary gate electrode; and etching thepreliminary gate electrode by a second etching process to form the gateelectrode while keeping the photo-resist on a surface of the preliminarygate electrode.
 3. The method for fabricating a lightly doped areaaccording to claim 1, wherein the patterning the gate metal layer toform the gate electrode comprises: applying photo-resist on the gatemetal layer, exposing the photo-resist using a mask, and developing thephoto-resist to form a preliminary gate electrode pattern; and etchingthe gate metal layer by a second etching process to form the gateelectrode.
 4. The method for fabricating a lightly doped area accordingto claim 2, wherein the etching the gate insulation layer to form thestepped structure, wherein the width of the gate electrode is smallerthan the width of the stepped structure, and the edge of the steppedstructure is not covered by the gate electrode comprises: etching thegate insulation layer for a first time by the first etching process toform a preliminary stepped structure after the gate metal layer isetched by the first etching process to form the preliminary gateelectrode.
 5. The method for fabricating a lightly doped area accordingto claim 4, wherein after the gate electrode is formed, the methodfurther comprises: etching the gate insulation layer for a second timeby the first etching process to form a final stepped structure.
 6. Themethod for fabricating a lightly doped area according to claim 5,wherein an etching rate of the first etching is higher than an etchingrate of the second etching.
 7. The method for fabricating a lightlydoped area according to claim 2, wherein the etching the gate insulationlayer to form the stepped structure, wherein the width of the gateelectrode is smaller than the width of the stepped structure, and theedge of the stepped structure is not covered by the gate electrodecomprises: etching the gate insulation layer by the first etchingprocess to form the stepped structure after the gate electrode isformed.
 8. The method for fabricating a lightly doped area according toclaim 2, wherein the first etching process is a dry etching process, andthe second etching process is a wet etching process.
 9. The method forfabricating a lightly doped area according to claim 1, wherein the gateinsulation layer is made of silicon nitride or silicon oxide.
 10. Themethod for fabricating a lightly doped area according to claim 1,wherein a width of an area of the stepped structure not covered by thegate electrode is equal to an expected width of the lightly doped area.11. The method for fabricating a lightly doped area according to claim1, wherein a thickness of an area of the gate insulation layer otherthan the stepped structure is smaller than 800 angstroms.
 12. The methodfor fabricating a lightly doped area according to claim 2, whereinbefore the poly-silicon layer is doped by the doping process using thegate electrode and the gate insulation layer with the stepped structureas the mask to form the lightly doped area and the heavily doped area,the method further comprises: removing the remaining photo-resist. 13.The method for fabricating a lightly doped area according to claim 1,wherein the poly-silicon layer is an un-doped poly-silicon layer beforethe poly-silicon layer is doped by the doping process using the gateelectrode and the gate insulation layer with the stepped structure asthe mask to form the lightly doped area and the heavily doped area. 14.The method for fabricating a lightly doped area according to claim 3,wherein the etching the gate insulation layer to form the steppedstructure, wherein the width of the gate electrode is smaller than thewidth of the stepped structure, and the edge of the stepped structure isnot covered by the gate electrode comprises: etching the gate insulationlayer by a first etching process to form the stepped structure after thegate electrode is formed.
 15. The method for fabricating a lightly dopedarea according to claim 3, wherein the second etching process by a wetetching process.
 16. The method for fabricating a lightly doped areaaccording to claim 3, wherein before the poly-silicon layer is doped bythe doping process using the gate electrode and the gate insulationlayer with the stepped structure as the mask to form the lightly dopedarea and the heavily doped area, the method further comprises: removingthe remaining photo-resist.
 17. A thin film transistor, comprising thelightly doped area fabricated in the method for fabricating a lightlydoped area according to claim 1, wherein the thin film transistorfurther comprises: a substrate, and a poly-silicon layer, a gateinsulation layer with a stepped structure, a gate electrode formed insequence on the substrate, wherein a width of the gate electrode issmaller than a width of the stepped structure, and an edge of thestepped structure is not covered by the gate electrode; and a width ofthe lightly doped area is equal to a width of an area of the steppedstructure not covered by the gate electrode.
 18. A thin film transistorarray substrate, comprising a plurality of the thin film transistorsaccording to claim 17.